1. Field of the Invention
The invention is related to semiconductor devices and methods of manufacturing semiconductor devices. Particularly, the invention is related to scalable quantum well devices and methods for manufacturing the same.
2. Description of the Related Technology
Continued physical scaling of mainstream silicon CMOS (complementary metal oxide semiconductor) technology has boosted the performance of the silicon devices in the last 40 years. However, even the benefits of the recently introduced new materials like high-k dielectrics and metal gates cannot guarantee that the race towards smaller devices will still be interesting in terms of performance enhancement beyond the 22 nm node.
A possible solution, at least for the next technology nodes, could be the introduction of new channel materials with higher carrier mobility. III-V compounds such as InSb, InAs, and InGaAs with high electron mobility are very promising materials and possible solutions for Si CMOS beyond 22 nm.
Besides their improved transport properties, the III-V compound semiconductors have also the advantage of well established manufacturing techniques used already in the fabrication of devices for microwave frequency communications and radar applications such as MESFET (metal epitaxial semiconductor field effect transistor), HEMT (high electron mobility transistor) and HBT (heterojunction bipolar transistor).
Device architectures inspired by the classical HEMT have been disclosed in the literature. However, the disclosed devices include recessed (cavity shaped groove) gate and/or T-shape gate configurations that are less suitable for scaling. Moreover, fabricating recess structures in the immediate vicinity of the gate and the channel layer can lead to damage which causes further performance loss or unstable operation of the device.
Therefore, despite the advances in the art, there is a need for providing a quantum well device with a scalable architecture for beyond 22 nm CMOS.